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PICDEM TM Lab Development Board User’s Guide
The audible frequency range is between 20-20000Hz. Therefore, the Timing()
delays from a maximum of 4.096 mS (244.1Hz) to a minimum of 1.536 mS (651Hz).
These values are determined using the internal instruction clock (F OSC /4) as the TMR0
clock source with a prescaler of 1:16. Other values could easily be used as long as the
frequency of the PWM remains within the audible range.
The software flowchart for this lab is shown in Figure 5-6.
FIGURE 5-6:
MAIN() SOFTWARE CONTROL LOOP FLOWCHART FOR
ADC LAB 2
main()
Global variables initialized:
? 8-bit variable TMR0_preload will be used to vary the
delay in Timing() to alter the frequency of the
PWM output on RC0
Initialize()
Get_Inputs()
Loop Forever
Decide()
Do_Outputs()
Timing()
The Initialize() configures the peripherals as follows:
? Ports
- Clear PORTB.
- Configure pin 13 as an analog input (using TRISB4).
- Clear the PORTC register.
- Configure RC0 pin as digital output.
? Timer0
- Select the F OSC /4 internal instruction clock as the Timer0 clock source.
- Increment TMR0 on the low-to-high transition of F OSC /4.
- Assign the prescaler to Timer0 and configure at a rate of 1:16.
? ADC
- Select ADC conversion clock F RC.
- Configure voltage reference using V DD .
- Select channel 10 as the ADC input channel (Pin 13: RB4/AN10).
- Select result format left justified (10-bit result in ADRESH<7:0> and
ADRESL<7:6>).
- Turn on ADC module.
DS41369A-page 86
? 2009 Microchip Technology Inc.
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